The present invention relates to an imaging apparatus having column-parallel analog-to-digital converters and a camera including the imaging apparatus.
In many cases, typical solid-state imaging apparatuses, each having column-parallel analog-to-digital converters, include counter-ramp analog-to-digital converters utilizing single-slope integration.
FIG. 1 illustrates the structure of an imaging apparatus having counter-ramp analog-to-digital converters utilizing single-slope integration.
FIG. 2 is a timing chart explaining the operation of the apparatus in FIG. 1.
The operation of the apparatus in FIG. 1 will now be described in relation to the timing chart of FIG. 2.
Unit pixels 1 for photoelectrically converting external light into electrical signals are arranged in a matrix to constitute a pixel array 2. It is assumed that a vertical selection circuit 3 selects a certain row in the pixel array 2.
A pixel in the selected row outputs a pixel signal (hereinafter, a pixel output signal S1) through a vertical signal line vs1 extending along the columns of the pixel array 2. The vertical signal line vs1 is connected to one input terminal (positive terminal) of a comparator 4 disposed for each column. The other terminal (negative terminal) of the comparator 4 receives an output signal nslope from a digital-to-analog (D/A) converter 5, the output signal being an analog signal obtained in response to a clock signal clk.
It is assumed that when the pixel output signal S1 transmitted through the vertical signal line vs1 is lower in level than the output signal nslope of the D/A converter 5, an output signal ncompout of the comparator 4 becomes low (“L”), whereas when the pixel output signal S1 of the vertical signal line vs1 is higher in level than the output signal nslope of the D/A converter 5, the output signal ncompout of the comparator 4 becomes high (“H”).
The output signal ncompout of the comparator 4 is supplied to an n-bit counter 6. The n-bit counter 6 increases or decreases a count value in response to the clock signal clk. FIG. 2 shows a case where the count value decreases by one.
The n-bit counter 6 resets its count value to an initial value iinit in response to a reset signal rst. When the output signal ncompout of the comparator 4 becomes high, the n-bit counter 6 stops increasing or decreasing the count value and holds the count value (denoted by “i” in FIG. 2).
This count value is output as n-bit output data [n−1:0] from the n-bit counter 6. The output of the n-bit counter 6 and outputs of other counters in other columns are sequentially output.